//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//+
//+   Copyright (c) CML Microsystems Plc 2015
//+
//+   This firmware was designed by CML Microcircuits (UK) Ltd, based on
//+   UK originated technology and is only intended for use on CML’s  Evaluation kits.
//+
//+   The supply and use of this Firmware is subject to CML's
//+   Licence Agreement, a copy of which can be obtained from CML on request.
//+
//+   Contact details:
//+   Technical:  techsupport@cmlmicro.com
//+   Sales:  sales@cmlmicro.com
//+
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++



#ifndef __SETTINGS_H_
#define __SETTINGS_H_

#include "Registers.h"


//CONFIGURATION


//-------------------------------------------------------------------
//
//! 		PROGRAMMING REGISTER CONFIGURATION VALUES
//
//-------------------------------------------------------------------

///PROGRAM BLOCK 1 CLOCK CONTROL
///Set to 19.2MHz
#define  P1_2_VAL		 40			//19.2MHz
#define  P1_3_VAL		208			//19.2MHz
#define  P1_4_VAL	   0x41			//19.2MHz
#define  P1_5_VAL		 78			//19.2MHz



//-------------------------------------------------------------------
//
//! 		CONFIGURATION VARIABLES
//
//-------------------------------------------------------------------

//! GENERAL PARAMETERS
#define FI_OPENDIALOG_ENABLE	TRUE
#define FI_PC_PATH 		"c:\\Data\\fi\\7261-1.3.0.1.h"		///<Full path of the location of the FI in the PC, should not
															///<use Program Files(it requires administrative privileges)

#define DEFAULT_OPT		0			///<Value 0 for enabling the menu selection, otherwise runs the selection with that value
#define DEBUG_DISP  	TRUE		///<Depending on the frequency the display should be disable (in case of overflows or underflows)

#define CBUSPORT		CBUS1		///<CBUS port to use

#define NSAMPLES		15000		///<Number of samples to capture


#define CFG_WAV_FILE		1
#define CFG_TEXT_FILE		2
#define CFG_BIN_FILE		3

#define CFG_IN_FILE			CFG_TEXT_FILE
#define CFG_OUT_FILE		CFG_TEXT_FILE

#define USE_WAV_FILES 	TRUE	//FIXME REMOVE 		///<Use WAV files instead of data files
//If Wav files TRUE, configure the following variables
#define WAV_CHANNELS		1			///<Use 1 mono, 2 stereo						//BY DEFAULT 1 DO NOT CHANGE IT
#define WAV_BITSPERSAMPLE  	16			///<Use 8 or 16 bits per sample				//BY DEFAULT 16 DO NOT CHANGE IT
#define WAV_SAMPLERATE		8000		///<Set the sample rate of the wav file


//! FOR CUSTOM OPERATIONS

//#define MODE_TYPE_VAL			MODE_HALF_TRANSC				///<Set the mode to run Disabled
#define MODE_AUDIO_SRC_VAL		MODE_AUDIO_SRC_CBUS				///<Set the audio source. Check mode register values
#define MODE_AUDIO_DST_VAL		MODE_AUDIO_DST_CBUS				///<Set the audio destination. Check mode register values

#define INPUT_TYPE_VAL			INPUT_TYPE_PACKED_G279A//INPUT_TYPE_16BIT_SIGNED_PCM//INPUT_TYPE_PACKED_G279A//INPUT_TYPE_UNPACKED_CVSD//INPUT_TYPE_16BIT_SIGNED_PCM			///<Set the input type for custom operations. Check input register values
#define OUTPUT_TYPE_VAL			OUTPUT_TYPE_PACKED_CVSD//OUTPUT_TYPE_PACKED_CVSD//OUTPUT_TYPE_UNPACKED_G279A//OUTPUT_TYPE_16BIT_SIGNED_PCM	///<Set the output type for custom operations. Check output register values

#define INPUT_RATE_VAL			RATE_8KHZ						///<Set input frequency rate if applicable. Check input register values
#define OUTPUT_RATE_VAL			RATE_32KHZ						///<Set output frequency rate if applicable. Check output register values

#define ANAOUT_CONF_VAL			ANAOUT_DAC_PWR | ANAOUT_DRVPWR | SPKR2_PWR	///<Set the output configuration for the ANAOUT_CONF Register. Power ups DAC, channels,etc. Check ANAOUT_CONF register values
#define ANAOUT_COARSE_GAIN_VAL	0								///<Set the output coarse gain. Check ANAOUT_COARSE_GAIN register
#define ANAIN_CONF_VAL			ADC_PWR	| ANAIN_PWR				///<Set the input configuration for the ANAIN_CONF register. Power ups ADC, etc. Check ANAIN_CONF register values.
#define ANAIN_COARSE_GAIN_VAL	0								///<Set the input coarse gain. Check ANAIN_COARSE_GAIN register.



//NOTE IMPORTANT FOR THE CASE OF TRANSCODER THAT REQUIRES TO SEND SAMPLES FROM A FILE AND STORE SAMPLES IN ANOTHER FILE
//		THROUGH THE USB (THE SPEED OF THE USB IS LIMITED, AND NOT CAPABLE TO MANAGE THE THROUGHPUT REQUIRED FOR A PROPER
//		OPERATION, THE COMMUNICATION BETWEEN PC AND PE0003 IS DONE BY MESSAGES AND REDUCES THE SPEED OF 3MBITS)
// 		THE EXAMPLE MAKE USE OF THE BIG STATIC BUFFERS IN MEMORY, THIS LIMITS THE NUMBER OF SAMPLES TO CAPTTURE TO
// 		THE STATIC BUFFERS SIZE. THERE ARE POSSIBILITIES OF OPTIMIZATION BY USING DEDICATED OPERATIONS WITHOUT MESSAGES
// 		AND EVEN

//ANOTHER EXAMPLE HAS BEING PROGRAM TO MAXIMIZE THE SPEED OF THE PE0003 TO BE ABLE TO CAPTURE SAMPLES AND STORE BIG
//CHUNKS OF DATA. THIS EXAMPLE MAKE USE OF THE 2ND CORE OF THE LPC4330 AND A SDCARD TO STORE THE SAMPLES


//-------------------------------------------------------------------
//
//! 		FIX VALUES
//
//-------------------------------------------------------------------

#define INBUFFER_SIZE		100		///<Size small bufferIn to hold the samples
#define OUTBUFFER_SIZE		100		///<Size small bufferOut to hold the samples
#define	WARNING_FIFO_LEVEL	126		///<Sets a limit in the level of the FIFO.If the FIFO reach that levels a error message is displayed
#define MAX_FIFO_SIZE		127		///<Size of the FIFO

//FIXME DANIEL SET TO A BIG PORTION
#define INSTATICBUFFER_SIZE		15000	///<Size of the static bufferIn, use it for full-duplex.
#define OUTSTATICBUFFER_SIZE	15000	///<Size of the static bufferOut, use it for full-duplex.




#endif /* __SETTINGS_H_ */
